The sigma-delta technology is of great interest for realizing linear, accurate and simple analog-to-digital converters. Sigma-delta coders and decoders generally require the use of decimation circuits requiring a great number of electronic components. For that reason, decimation circuits are embodied by means of Very Large Scale Technology (VLSI) components.
FIG. 1 shows the traditional basic structure of a analog-to-digital converter using a sigma-delta converter (101) for converting an analog input signal existing on lead 110 into a train of sigma-delta pulses on a lead 120. The train of sigma-delta pulse comprises a high level of out-of-band quantization noise which is then entered into a decimation circuit 104 in order to convert the sigma-delta pulses into a sequence of Pulse Code Modulation (PCM) samples on lead 140. For that purpose, decimation circuit 104 includes a low-pass digital filter 102 for suppressing the above out-of-band quantization noise and for avoiding in-band aliasing during the decimation process. Decimation circuit 104 also includes a specific decimation element which samples down the output signal of the low-pass filter. This is simply achieved by taking one sample over N samples. N is called the "decimation factor" of the decimation process.
FIG. 2 illustrates the different signal spectra which are involved in sigma-delta conversion and decimation processes. FIG. 2a shows a spectrum of a typical band-limited analog input signal which is carried by lead 110 and which is to be coded. FIG. 2b shows the spectrum of the corresponding train of sigma-delta pulses existing on lead 120 and resulting from the sigma-delta conversion process. As mentioned above, the sigma-delta bit stream has a high level of out-of-band quantization noise which periodically extends over the whole band with a period fs which is equal to the value of the sigma-delta modulation frequency. The dotted lines in FIG. 2c illustrate the frequency response of the low-pass filter. The resulting filtered signal has a spectrum which is shown in FIG. 2d. Finally, FIG. 2e illustrates the spectrum of the PCM signal which exists at the output of decimation circuit 104. The PCM words are generated at a frequency of fs/N.
Generally speaking, the value of the decimation factor N is chosen by considering first the signal/noise ratio which is required and also the bandwidth of the input signal. Since sigma-delta coders and decoders are likely to be used in a wide variety of different applications, it is highly desirable to provide a sigma-delta coder having a variable, programmable decimation factor as will be shown in the following examples which have been chosen in the telecommunication field. A first example can be found by considering a V32 modem or DCE. The echo estimation and cancellation techniques involved in such modems require a signal-to-noise ratio which is at least equal to 80 dB. FIG. 3 shows a table indicating approximate theoretical values of the signal-to-noise ratio as a function of the bandwidth of the input signal fb and also the oversampling frequency fs. It appears in the table that a signal-to-noise ratio of 80 dB is provided in the case where the ratio fs/fb (i.e., the "oversampling factor") is at least equal to 300. Since the bandwidth of such modems is about 3 kHz, the oversampling frequency must be at least equal to 900 khz. If the V32 modem uses four samples per bit time, the decimation factor appears to be equal to 300/4=75. Conversely, when considering a base-band modem which is intended to be connected to a digital network, the bandwidth should be at least equal to 72 kHz. It results that the preceding oversampling ratio (300) would lead to an oversampling frequency of at least 20 MHz (300.times.72 kHz) which is practically unattainable. However, since such a base-band modem does not involve highly sophisticated echo-cancellation techniques, a signal-to-noise ratio of 60 dB appears to be sufficient. FIG. 3 shows that a signal-to-noise ratio of 60 dB corresponds to an oversampling ratio of at least 64 which results in a decimation factor of 64/2=32 (assuming that the modem is embodied with a sigma-delta coder using two samples per bit time).
Therefore, since the oversampling frequency is compelled to be limited by the actual technology and since the value fb is likely to vary to a large extent when considering different applications (modems, voice processing system, audio etc . . . ) it is highly desirable to provide a sigma-delta coder which has a decimation factor that is variable and adjustable by the user. Since the sigma-delta converter is intended to be embodied in costly high sophisticated VLSI technology, it is also desirable that the same chip be able to satisfy a wide variety of users.